IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-03-05 17:30
Debugging Support for Synchronization of Parallel Execution in System Level Designs
Hiroki Harada, Tasuku Nishihara, Takeshi Matsumoto (Tokyo University), Masahiro Fujita (Tokyo University/JST) CPSY2008-94 DC2008-85
Abstract (in Japanese) (See Japanese page) 
(in English) There are many high-level designs contain parallel execution, synchronization, or communication, and they are often error-prone. In this work, we propose a debugging support method for designs with improper synchronization. We derive a safe condition in which synchronization works properly under the target design. The experiment with an elevator controller containing parallel executions shows that we can easily check whether synchronization works as the designer intended or not, by using the derived condition.
Keyword (in Japanese) (See Japanese page) 
(in English) System level design / Synchronization verification / Symbolic simulation / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 464, DC2008-85, pp. 37-42, March 2009.
Paper # DC2008-85 
Date of Issue 2009-02-26 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2008-94 DC2008-85

Conference Information
Conference Date 2009-03-05 - 2009-03-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Sado Island Integrated Development Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2009 
Paper Information
Registration To DC 
Conference Code 2009-03-DC-CPSY-SLDM-EMB 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Debugging Support for Synchronization of Parallel Execution in System Level Designs 
Sub Title (in English)  
Keyword(1) System level design  
Keyword(2) Synchronization verification  
Keyword(3) Symbolic simulation  
1st Author's Name Hiroki Harada  
1st Author's Affiliation Tokyo University (Tokyo University)
2nd Author's Name Tasuku Nishihara  
2nd Author's Affiliation Tokyo University (Tokyo University)
3rd Author's Name Takeshi Matsumoto  
3rd Author's Affiliation Tokyo University (Tokyo University)
4th Author's Name Masahiro Fujita  
4th Author's Affiliation Tokyo University/JST (Tokyo University/JST)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2009-03-05 17:30:00 
Presentation Time 30 
Registration for DC 
Paper # IEICE-CPSY2008-94,IEICE-DC2008-85 
Volume (vol) IEICE-108 
Number (no) no.463(CPSY), no.464(DC) 
Page pp.37-42 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2009-02-26,IEICE-DC-2009-02-26 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan