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| Presentation | 2009-02-16 11:30 Decimal adder using abacus architecture and its application to residue arithmetic Tadahito Iijima, Shugang Wei (Gunma Univ.)  DC2008-71 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In a decimal number system, arithmetic circuits are implemented by using the binary number representations well known as BCD codes, so that binary arithmetic circuits can be used for the realization of a decimal arithmetic circuit. However, the carry propagation will limit the speed of operations such as addition, subtraction and multiplication. In this paper, the abacus architecture is introduced to achieve high speed arithmetic circuits for the decimal number system. First we give a fast calculation method to obtain the carries in additions in the abacus architecture. Then we present residue addition algorithm using the abacus addition. The design and simulation results show that the proposed decimal arithmetic circuits based on the abacus architecture are high speed compared to the binary methods and our previous works. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | abacus / decimal addition / residue number system / VHDL / synopsys / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 431, DC2008-71, pp. 19-23, Feb. 2009. | |
| Paper # | DC2008-71 | |
| Date of Issue | 2009-02-09 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2008-71 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2009-02-16 - 2009-02-16 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2009-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Decimal adder using abacus architecture and its application to residue arithmetic |
| Sub Title (in English) | |
| Keyword(1) | abacus |
| Keyword(2) | decimal addition |
| Keyword(3) | residue number system |
| Keyword(4) | VHDL |
| Keyword(5) | synopsys |
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| 1st Author's Name | Tadahito Iijima |
| 1st Author's Affiliation | Gunma University (Gunma Univ.) |
| 2nd Author's Name | Shugang Wei |
| 2nd Author's Affiliation | Gunma University (Gunma Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-02-16 11:30:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2008-71 |
| Volume (vol) | vol.108 |
| Number (no) | no.431 |
| Page | pp.19-23 |
| #Pages | 5 |
| Date of Issue | 2009-02-09 (DC) |
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