Paper Abstract and Keywords |
Presentation |
2009-01-30 09:40
Foreknown Regularity Arithmetic Processing Unit Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-111 CPSY2008-73 RECONF2008-75 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The paper proposes a method of designing an arithmetic unit based on the regularity of the output depending on input pattern. The advantages of this method are reduced number of gates without sacrificing high speed calculation and easy modularization scheme for high precision arithmetic unit. The soundness of this method is confirmed by the implementation on FPGA. This circuit design method based on foreknown regularity between input and output pattern can be applied not only to arithmetic operation such as addition/subtraction, but also to other circuit units. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Adder/Subtractor / Regularity of the Arithmetic / High-speed Arithmetic method / Modularizing / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 412, VLD2008-111, pp. 117-122, Jan. 2009. |
Paper # |
VLD2008-111 |
Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2008-111 CPSY2008-73 RECONF2008-75 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2009-01-29 - 2009-01-30 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2009-01-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Foreknown Regularity Arithmetic Processing Unit |
Sub Title (in English) |
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Keyword(1) |
Adder/Subtractor |
Keyword(2) |
Regularity of the Arithmetic |
Keyword(3) |
High-speed Arithmetic method |
Keyword(4) |
Modularizing |
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1st Author's Name |
Jin Sato |
1st Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
2nd Author's Name |
Tsugio Nakamura |
2nd Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
3rd Author's Name |
Narito Fuyutsume |
3rd Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
4th Author's Name |
Hiroshi Kasahara |
4th Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
5th Author's Name |
Teruo Tanaka |
5th Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
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Speaker |
Author-1 |
Date Time |
2009-01-30 09:40:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-111, CPSY2008-73, RECONF2008-75 |
Volume (vol) |
vol.108 |
Number (no) |
no.412(VLD), no.413(CPSY), no.414(RECONF) |
Page |
pp.117-122 |
#Pages |
6 |
Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |