Paper Abstract and Keywords |
Presentation |
2009-01-30 14:10
Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.) VLD2008-119 CPSY2008-81 RECONF2008-83 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits, each sub-circuit is assigned to a context, and the MC-FPGA sequentially executes all the contexts one by one. So, the total execution delay is the sum of the delays of all the contexts. It is, therefore, said that the total execution delay of the MC-FPGA increases proportional to the number of contexts used. However, in this paper, we show that the total execution delay remains constant if a shift-register-type temporal communication module (SR-TCM) is used instead of D-FlipFlop (D-FF) to implement sequential circuits. The SR-TCM is used not only for sequential circuit like D-FF, but also for signal communication from preceding context to succeeding contexts. In order to quantify the execution delay, a MC-FPGA named Flexible Processor (FP), which equips the SR-TCM, have been designed and fabricated in 90nm CMOS process technology. From the measurement results, the total execution delay of the FP was kept constant regardless of the number of contexts used. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Multi-Context / FPGA / Temporal Signal Communication / Temporal Circuit Partitioning / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 414, RECONF2008-83, pp. 165-170, Jan. 2009. |
Paper # |
RECONF2008-83 |
Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-119 CPSY2008-81 RECONF2008-83 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2009-01-29 - 2009-01-30 |
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(See Japanese page) |
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Paper Information |
Registration To |
RECONF |
Conference Code |
2009-01-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation |
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Multi-Context |
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FPGA |
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Temporal Signal Communication |
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Temporal Circuit Partitioning |
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1st Author's Name |
Naoto Miyamoto |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Tadahiro Ohmi |
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Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2009-01-30 14:10:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2008-119, CPSY2008-81, RECONF2008-83 |
Volume (vol) |
vol.108 |
Number (no) |
no.412(VLD), no.413(CPSY), no.414(RECONF) |
Page |
pp.165-170 |
#Pages |
6 |
Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |
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