IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-01-30 12:20
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm efficiently searches for an optimal selection of the number and bit-size of buses, CPU-bus connection topology, and the priority of each CPU subject to the time constraint for given embedded applications. It is necessary to estimate the running time of applications with taking into consideration the effect of memory access conflict. Before taking into consideration the effect of memory access conflict, our approach removes configurations which violate the constraints. By reducing the design space in this way we can obtain an optimal configuration in shorter time. Our algorithm is 8.55 faster compared to the exhaustive approach.
Keyword (in Japanese) (See Japanese page) 
(in English) MPSoC / Bus Architecture Optimization / Embedded System / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 412, VLD2008-115, pp. 141-146, Jan. 2009.
Paper # VLD2008-115 
Date of Issue 2009-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-115 CPSY2008-77 RECONF2008-79

Conference Information
Conference Date 2009-01-29 - 2009-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2009-01-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems 
Sub Title (in English)  
Keyword(1) MPSoC  
Keyword(2) Bus Architecture Optimization  
Keyword(3) Embedded System  
1st Author's Name Harunobu Yoshida  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Nozomu Togawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Tatsuo Ohtsuki  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Masayoshi Tachibana  
5th Author's Affiliation Kochi University of Technology (KUT)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2009-01-30 12:20:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-115,IEICE-CPSY2008-77,IEICE-RECONF2008-79 
Volume (vol) IEICE-108 
Number (no) no.412(VLD), no.413(CPSY), no.414(RECONF) 
Page pp.141-146 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-01-22,IEICE-CPSY-2009-01-22,IEICE-RECONF-2009-01-22 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan