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| Presentation | 2009-01-29 09:05 Evaluation of a Multicore Reconfigurable Architecture Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.)  VLD2008-92 CPSY2008-54 RECONF2008-56 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection network is introduced. A comparision of a tile-based architecture and the proposed multicore architecture in terms of performance is examined. Then, an evaluation with different core sizes is implemented in order to find out how the size of cores in a homogeneous system influences on the performance and the internal fragmentation of target applications. Using real applications implemented on the proposed architecture in which cores are based on NEC Electronics' DRP-1, the evaluation result shows that the size of core is a trade-off between throughput and resource usage, and the size of two or three DRP tiles is an appropriate choice for many cases. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multicore Reconfigurable Architecture / Tile-based Architecture / Core Size / Network-On-Chip / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 414, RECONF2008-56, pp. 7-12, Jan. 2009. | |
| Paper # | RECONF2008-56 | |
| Date of Issue | 2009-01-22 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2008-92 CPSY2008-54 RECONF2008-56 |
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| Conference Information | |
| Committee | VLD CPSY RECONF IPSJ-SLDM |
| Conference Date | 2009-01-29 - 2009-01-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-01-VLD-CPSY-RECONF-SLDM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of a Multicore Reconfigurable Architecture |
| Sub Title (in English) | |
| Keyword(1) | Multicore Reconfigurable Architecture |
| Keyword(2) | Tile-based Architecture |
| Keyword(3) | Core Size |
| Keyword(4) | Network-On-Chip |
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| 1st Author's Name | Vu Manh Tuan |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Hiroki Matsutani |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Naohiro Katsura |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-01-29 09:05:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2008-92, CPSY2008-54, RECONF2008-56 |
| Volume (vol) | vol.108 |
| Number (no) | no.412(VLD), no.413(CPSY), no.414(RECONF) |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2009-01-22 (VLD, CPSY, RECONF) |
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