| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2009-01-29 10:05 Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.)  VLD2008-94 CPSY2008-56 RECONF2008-58 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, the examples which use FPGA for the HPC use are increasing. We propose FPGA array which accumulated a lot of small cards with the three-dimensional I/O that installed large-scale FPGA. The FPGA array is suited to the scalable design, and it is possible to control from the host PC easily. In this paper, we implemented the arithmetic circuit which calculated Poisson equation by the finite difference method in floating point number into the FPGA array, and the performance and power consumption are presented. In addition, we have designed arithmetic circuits worked in parallel, and show a number of FPGA array to achieve 1[TFlops]. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / HPC / Scalable / hw/sw complex / Poisson epuation / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 414, RECONF2008-58, pp. 19-24, Jan. 2009. | |
| Paper # | RECONF2008-58 | |
| Date of Issue | 2009-01-22 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2008-94 CPSY2008-56 RECONF2008-58 |
|
| Conference Information | |
| Committee | VLD CPSY RECONF IPSJ-SLDM |
| Conference Date | 2009-01-29 - 2009-01-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-01-VLD-CPSY-RECONF-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | HPC |
| Keyword(3) | Scalable |
| Keyword(4) | hw/sw complex |
| Keyword(5) | Poisson epuation |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazuki Sato |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
| 2nd Author's Name | Baatarsuren Bars |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
| 3rd Author's Name | Masatoshi Sekine |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2009-01-29 10:05:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2008-94, CPSY2008-56, RECONF2008-58 |
| Volume (vol) | vol.108 |
| Number (no) | no.412(VLD), no.413(CPSY), no.414(RECONF) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2009-01-22 (VLD, CPSY, RECONF) |
[Return to Top Page]