IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-01-29 10:30
FPGA Implementation of Metastability-based True Random Number Generator
Hisashi Hata, Shuichi Ichikawa (TUT) VLD2008-95 CPSY2008-57 RECONF2008-59
Abstract (in Japanese) (See Japanese page) 
(in English) Metastability of RS latch is utilizable as an entropy source for true random number generators (TRNG). This kind of TRNG is comprised of logic gates, which can be integrated into a logic LSI. Though latch-based TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation with common FPGA technology. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness, minimizing the clock skew and load imbalance of internal nodes. The quality and throughput are further improved by XOR'ing the output of 32--128 latches. The derived design was implemented with Xilinx Virtex4 FPGA (XC4VFX20), and passed NIST test without post-processing. A TRNG of 128 latches occupies 290 slices, while achieving 8.33 Mbps throughput.
Keyword (in Japanese) (See Japanese page) 
(in English) random number generator / synchronous digital circuit / FPGA / metastability / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 414, RECONF2008-59, pp. 25-30, Jan. 2009.
Paper # RECONF2008-59 
Date of Issue 2009-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-95 CPSY2008-57 RECONF2008-59

Conference Information
Committee VLD CPSY RECONF IPSJ-SLDM  
Conference Date 2009-01-29 - 2009-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2009-01-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) FPGA Implementation of Metastability-based True Random Number Generator 
Sub Title (in English)  
Keyword(1) random number generator  
Keyword(2) synchronous digital circuit  
Keyword(3) FPGA  
Keyword(4) metastability  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hisashi Hata  
1st Author's Affiliation Toyohashi University of Technology (TUT)
2nd Author's Name Shuichi Ichikawa  
2nd Author's Affiliation Toyohashi University of Technology (TUT)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2009-01-29 10:30:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2008-95,IEICE-CPSY2008-57,IEICE-RECONF2008-59 
Volume (vol) IEICE-108 
Number (no) no.412(VLD), no.413(CPSY), no.414(RECONF) 
Page pp.25-30 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2009-01-22,IEICE-CPSY-2009-01-22,IEICE-RECONF-2009-01-22 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan