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| Presentation | 2009-01-22 10:00 A study of a bit-block circuit that realizes a 14-bit, 50MS/s, and 1.8V operational ADC Keiichirou Mizutani, Yasuhiro Sugimoto (Chuo Univ.)  CAS2008-66 NLP2008-96 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In a high-speed and high-precision pipelined A-D converter, an operational amplifier with high gain and high frequency bandwidth is needed especially in the first bit-block circuit. However, it becomes difficult to achieve high gain and high frequency bandwidth for such an amplifier which utilizes reduced size of transistors in recent advanced LSI process because transistor’s breakdown voltage becomes extremely low. To alleviate the discrepancy, the multi-stage approach which connects amplifier stages in series is commonly used, however, this approach does not work well when it is applied to an amplifier in a bit-block of a pipelined A-D converter because near 100 % of negative feedback is applied to the amplifier. In that case, the amplifier becomes unstable due to the lack of the phase margin. In this paper, we introduced a new phase compensation scheme for the three-stage amplifier to obtain stability, and use it as an amplifier in the bit-block of a pipelined A-D converter. The simulation shows the enough evidence for the bit-block circuit to become the one of the first bit-block of a 14-bit, 50 MS/s and 1.8 V pipelined A-D converter. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | AD converter / operational amplifier / phase compensation / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 388, CAS2008-66, pp. 19-24, Jan. 2009. | |
| Paper # | CAS2008-66 | |
| Date of Issue | 2009-01-15 (CAS, NLP) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2008-66 NLP2008-96 |
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| Conference Information | |
| Committee | CAS NLP |
| Conference Date | 2009-01-22 - 2009-01-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2009-01-CAS-NLP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study of a bit-block circuit that realizes a 14-bit, 50MS/s, and 1.8V operational ADC |
| Sub Title (in English) | |
| Keyword(1) | AD converter |
| Keyword(2) | operational amplifier |
| Keyword(3) | phase compensation |
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| 1st Author's Name | Keiichirou Mizutani |
| 1st Author's Affiliation | Chuo University (Chuo Univ.) |
| 2nd Author's Name | Yasuhiro Sugimoto |
| 2nd Author's Affiliation | Chuo University (Chuo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-01-22 10:00:00 |
| Presentation Time | 20 minutes |
| Registration for | CAS |
| Paper # | CAS2008-66, NLP2008-96 |
| Volume (vol) | vol.108 |
| Number (no) | no.388(CAS), no.389(NLP) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2009-01-15 (CAS, NLP) |
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