Paper Abstract and Keywords |
Presentation |
2008-11-19 11:15
An On-Chip Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio Susumu Kobayashi, Naoshi Doi (NEC Electronics Corp.) CPM2008-95 ICD2008-94 Link to ES Tech. Rep. Archives: CPM2008-95 ICD2008-94 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Decoupling Capacitance / Power Supply Noise / Power Dissipation / Layout Design / Simulation / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 302, ICD2008-94, pp. 37-42, Nov. 2008. |
Paper # |
ICD2008-94 |
Date of Issue |
2008-11-11 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CPM2008-95 ICD2008-94 Link to ES Tech. Rep. Archives: CPM2008-95 ICD2008-94 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2008-11-17 - 2008-11-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu Science and Research Park |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2008 ―New field of VLSI design― |
Paper Information |
Registration To |
ICD |
Conference Code |
2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An On-Chip Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio |
Sub Title (in English) |
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Keyword(1) |
Decoupling Capacitance |
Keyword(2) |
Power Supply Noise |
Keyword(3) |
Power Dissipation |
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Layout Design |
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Simulation |
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1st Author's Name |
Susumu Kobayashi |
1st Author's Affiliation |
NEC Electronics Corporation (NEC Electronics Corp.) |
2nd Author's Name |
Naoshi Doi |
2nd Author's Affiliation |
NEC Electronics Corporation (NEC Electronics Corp.) |
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Speaker |
Author-1 |
Date Time |
2008-11-19 11:15:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
CPM2008-95, ICD2008-94 |
Volume (vol) |
vol.108 |
Number (no) |
no.301(CPM), no.302(ICD) |
Page |
pp.37-42 |
#Pages |
6 |
Date of Issue |
2008-11-11 (CPM, ICD) |
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