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Paper Abstract and Keywords
Presentation 2008-11-18 11:20
A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains
Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology) VLD2008-82 DC2008-50
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents an optimization method for designing reconfigurable test wrappers for cores with multiple clock domains. By dividing test application into two steps considering the difference of test data volume in inter-domain tests and intra-domain tests, the proposed method can reduce test time compared to the previous wrapper designs for multi-clock domain cores.
Keyword (in Japanese) (See Japanese page) 
(in English) SoC test / wrapper design / multi-clock domain core / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 299, DC2008-50, pp. 133-138, Nov. 2008.
Paper # DC2008-50 
Date of Issue 2008-11-10 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-82 DC2008-50

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To DC 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains 
Sub Title (in English)  
Keyword(1) SoC test  
Keyword(2) wrapper design  
Keyword(3) multi-clock domain core  
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1st Author's Name Takashi Yoshida  
1st Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
2nd Author's Name Tomokazu Yoneda  
2nd Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
3rd Author's Name Hideo Fujiwara  
3rd Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
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Speaker Author-1 
Date Time 2008-11-18 11:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2008-82, DC2008-50 
Volume (vol) vol.108 
Number (no) no.298(VLD), no.299(DC) 
Page pp.133-138 
#Pages
Date of Issue 2008-11-10 (VLD, DC) 


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