| Paper Abstract and Keywords |
| Presentation |
2008-11-18 13:00
Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Rule-based equivalence checking of high-level design descriptions proves the equivalence of two high-level design descriptions by applying the equivalence rules in a bottomup manner. Since the previous work derives the equivalence of the internal variables based on their names, the method often fails to prove the equivalence when variable names are changed. This paper proposes a method for improving the accuracy of the rule-based equivalence checking by identifying potential internal equivalences using random simulation. Experimental results using an example design shows that the proposed method can prove the equivalence of the designs before and after a practical design optimization. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
System-level design / Formal verification / Internal equivalences / Random simulation / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 108, pp. 109-114, Nov. 2008. |
| Paper # |
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| Date of Issue |
2008-11-10 (VLD, DC) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
| Download PDF |
|
| Conference Information |
| Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date |
2008-11-17 - 2008-11-19 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kitakyushu Science and Research Park |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Design Gaia 2008 ―New field of VLSI design― |
| Paper Information |
| Registration To |
IPSJ-SLDM |
| Conference Code |
2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences |
| Sub Title (in English) |
|
| Keyword(1) |
System-level design |
| Keyword(2) |
Formal verification |
| Keyword(3) |
Internal equivalences |
| Keyword(4) |
Random simulation |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(8) |
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| 1st Author's Name |
Hiroaki Yoshida |
| 1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
| 2nd Author's Name |
Masahiro Fujita |
| 2nd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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| Speaker |
Author-1 |
| Date Time |
2008-11-18 13:00:00 |
| Presentation Time |
25 minutes |
| Registration for |
IPSJ-SLDM |
| Paper # |
VLD2008-78, DC2008-46 |
| Volume (vol) |
vol.108 |
| Number (no) |
no.298(VLD), no.299(DC) |
| Page |
pp.109-114 |
| #Pages |
6 |
| Date of Issue |
2008-11-10 (VLD, DC) |