Paper Abstract and Keywords |
Presentation |
2008-11-17 16:30
Evaluating the reliability of Highly Reliable Cell Circuits Keiichi Hotta, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) VLD2008-75 DC2008-43 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, the shrinking process causes transistor variation and growth of error rate. Highly Reliable Cells (HRCs) have been proposed to solve these problems. We need to evaluate reliability of them quantitatively,
because they are considered to be highly reliable. Although, there have been proposed several methods to evaluate the reliability, they cannot evaluate the reliability of circuits by HRCs accurately. Therefore, in this paper, we propose a new evaluation method for the reliability of circuits based on the fault probability of each transistor. The method can evaluate the reliablity of circuits by HRCs or the CMOS cells. The experimental results show that HRCs are more reliable than the CMOS cells. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
reliability evaluation / fault tolerance / transistor variation / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 298, VLD2008-75, pp. 91-96, Nov. 2008. |
Paper # |
VLD2008-75 |
Date of Issue |
2008-11-10 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2008-75 DC2008-43 |
|