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| Presentation | 2008-09-29 15:10 FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.)  VLD2008-49 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. In this paper, we design FFT filters and propose an algorithm to map them onto it automatically. For a given data point of an FFT filter, the algorithm generates a dedicated assembly code which represents a given FFT circuits for FE-GA. After implementing FFT filters to FE-GA, an editor called FEEditor reads the generated assembly code and implements its corresponding FFT filter on FE-GA. The proposed algorithm achieves automatic mapping of FFT filters of all data points within the range of the specification of FE-GA architecture. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | reconfigurable processor / FE-GA / FFT filter / filter mapping / mapping automation / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 224, VLD2008-49, pp. 13-18, Sept. 2008. | |
| Paper # | VLD2008-49 | |
| Date of Issue | 2008-09-22 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2008-49 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2008-09-29 - 2008-09-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Physical Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-09-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable processor |
| Keyword(2) | FE-GA |
| Keyword(3) | FFT filter |
| Keyword(4) | filter mapping |
| Keyword(5) | mapping automation |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryo Tamura |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Masayuki Honma |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Masao Yanagisawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Tatsuo Ohtsuki |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
| 6th Author's Name | Makoto Satoh |
| 6th Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
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| Speaker | Author-1 |
| Date Time | 2008-09-29 15:10:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2008-49 |
| Volume (vol) | vol.108 |
| Number (no) | no.224 |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2008-09-22 (VLD) |
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