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Paper Abstract and Keywords
Presentation 2008-09-26 11:00
Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β
Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34
Abstract (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Although some devices are commercially available, an evaluation results with real chips have been rarely reported.

MuCCRA (Multi-Context Configurable Reconfigurable Architecture) project aims to establish techniques to generate a cost effective low power DRPA for a given target application. MuCCAR-2 is the second prototype chip of MuCCRA project and
MuCCRA-2 $\beta$, which includes a PE and reconfiguration mechanism was also taped out as a prototype for evaluation. In this paper, we implemented three kinds of image processing applications on MuCCRA-2 $\beta$, and measured its frequency and power consumption. As a result, in case of executing nega/posi at 55.2 MHz of frequency, and of executing three applications at 49.5 MHz, 5.44 mW of power consumption was confirmed at the average.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor / Practice Evaluation / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 220, RECONF2008-34, pp. 69-74, Sept. 2008.
Paper # RECONF2008-34 
Date of Issue 2008-09-18 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2008-09-25 - 2008-09-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Okayama Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2008-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processor  
Keyword(2) Practice Evaluation  
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1st Author's Name Yoshiki Saito  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Masaru Kato  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Shotaro Saito  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Toru Sano  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Keiichiro Hirai  
5th Author's Affiliation Keio University (Keio Univ.)
6th Author's Name Takashi Nishimura  
6th Author's Affiliation Keio University (Keio Univ.)
7th Author's Name Takuro Nakamura  
7th Author's Affiliation Keio University (Keio Univ.)
8th Author's Name Satoshi Tsutsumi  
8th Author's Affiliation Keio University (Keio Univ.)
9th Author's Name Yohei Hasegawa  
9th Author's Affiliation Keio University (Keio Univ.)
10th Author's Name Hideharu Amano  
10th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2008-09-26 11:00:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2008-34 
Volume (vol) vol.108 
Number (no) no.220 
Page pp.69-74 
#Pages
Date of Issue 2008-09-18 (RECONF) 


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