Paper Abstract and Keywords |
Presentation |
2008-09-26 11:00
Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Although some devices are commercially available, an evaluation results with real chips have been rarely reported.
MuCCRA (Multi-Context Configurable Reconfigurable Architecture) project aims to establish techniques to generate a cost effective low power DRPA for a given target application. MuCCAR-2 is the second prototype chip of MuCCRA project and
MuCCRA-2 $\beta$, which includes a PE and reconfiguration mechanism was also taped out as a prototype for evaluation. In this paper, we implemented three kinds of image processing applications on MuCCRA-2 $\beta$, and measured its frequency and power consumption. As a result, in case of executing nega/posi at 55.2 MHz of frequency, and of executing three applications at 49.5 MHz, 5.44 mW of power consumption was confirmed at the average. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Dynamically Reconfigurable Processor / Practice Evaluation / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 220, RECONF2008-34, pp. 69-74, Sept. 2008. |
Paper # |
RECONF2008-34 |
Date of Issue |
2008-09-18 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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RECONF2008-34 |
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