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Paper Abstract and Keywords
Presentation 2008-09-26 13:50
Consideration of Combinational Circuit Mapping Method for Reconfigurable Device MPLD
Yutaro Oda, Kazuya Tanigawa, Tetsuo Hironaka, Naoki Hirakawa, Hiroaki Toguchi (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden) RECONF2008-37
Abstract (in Japanese) (See Japanese page) 
(in English) As a novel Field Programmable Gate Array(FPGA), MPLD has been proposed. The MPLD consists of MLUTs. which has functions as LUT, switch block, and memory. By placing and connecting the neighboring MLUTs, MPLD can behave like conventional FPGA. However, the circuit mapping method is different from FPGA because of the large architecture difference. herefore, development of a novel CAD to map a large circuit into MPLD is needed for practical use.
In this paper, a new CAD for MPLD is proposed. At first the conventional mapping method were investigated. Next, the method to map a circuit into MPLD was discussed. After that, the CAD for MPLD was developed by using C language which can map a combinational circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / MPLD / CAD / memory / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 220, RECONF2008-37, pp. 87-92, Sept. 2008.
Paper # RECONF2008-37 
Date of Issue 2008-09-18 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2008-09-25 - 2008-09-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Okayama Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2008-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Consideration of Combinational Circuit Mapping Method for Reconfigurable Device MPLD 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) MPLD  
Keyword(3) CAD  
Keyword(4) memory  
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1st Author's Name Yutaro Oda  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Kazuya Tanigawa  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tetsuo Hironaka  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Naoki Hirakawa  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
5th Author's Name Hiroaki Toguchi  
5th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
6th Author's Name Masayuki Sato  
6th Author's Affiliation Taiyo Yuden Co., Ltd. (Taiyo Yuden)
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Speaker Author-1 
Date Time 2008-09-26 13:50:00 
Presentation Time 30 minutes 
Registration for RECONF 
Paper # RECONF2008-37 
Volume (vol) vol.108 
Number (no) no.220 
Page pp.87-92 
#Pages
Date of Issue 2008-09-18 (RECONF) 


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