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| Presentation | 2008-09-26 13:20 A study of a fault-tolerant System using TFT method Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Univ. of Tsukuba)  RECONF2008-36 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper deals with a dependable computing system using a reconfigurable device. The work carried out for this purpose of this study involved the proposition of an fault-tolerant approach which covers general purpose LSI such as microprocessors. TFT, which is short for Tile-based Fault Tolerant approach, has the intermediate layer which makes the connection between physical circuit layout and logical circuit layout for use in partial and dynamic reconfiguration. The partial reconfiguration is effectively utilized for online replacement of failed circuits. An advantage of TFT is that there is no conflict with other fault-tolerant approaches, and therefore TFT is freely available in the construction of dependable systems. Experimental result demonstrates the SuperH RISC processor implementation and the effectiveness of our approach. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / Dependable computing / Partial Reconfiguration / Fault tolerance / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 220, RECONF2008-36, pp. 81-86, Sept. 2008. | |
| Paper # | RECONF2008-36 | |
| Date of Issue | 2008-09-18 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2008-36 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2008-09-25 - 2008-09-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okayama Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2008-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study of a fault-tolerant System using TFT method |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Dependable computing |
| Keyword(3) | Partial Reconfiguration |
| Keyword(4) | Fault tolerance |
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| 1st Author's Name | Atsuhiro Kanamaru |
| 1st Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
| 2nd Author's Name | Hiroyuki Kawai |
| 2nd Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
| 3rd Author's Name | Yoshiki Yamaguchi |
| 3rd Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
| 4th Author's Name | Moritoshi Yasunaga |
| 4th Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
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| Speaker | Author-3 |
| Date Time | 2008-09-26 13:20:00 |
| Presentation Time | 30 minutes |
| Registration for | RECONF |
| Paper # | RECONF2008-36 |
| Volume (vol) | vol.108 |
| Number (no) | no.220 |
| Page | pp.81-86 |
| #Pages | 6 |
| Date of Issue | 2008-09-18 (RECONF) |
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