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| Presentation | 2008-09-25 13:30 Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ)  RECONF2008-24 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, dynamically reconfigurable hardware has been attracted, the research becomes active, and quantitative evaluation for its availability is important. This paper describes an implementation of JPEG encoders on DAPDNA-2 which IPFlex Inc. developed, and its evaluation. We implemented a converter for color specification system and a two-dimensional DCT to DNA which is a parallel processing engine with dynamic reconfiguration in DAPDNA-2, and implemented other parts of JPEG encoder to DAP which is a RISC processor core in DAPDNA-2. For efficient use of hardware resources, we implemented the circuits in two or four parallel. Furthermore we tried to reduce control processing time of dynamic reconfiguration. As results of evaluation, we confirmed that the processing speed on a DNA was same as the speed on a PC (Pentium4 2.8GHz) or faster in case of an input image size is large, and energy consumption of DNA was about 1/50 compared with the PC. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable Processor / JPEG Encode / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 220, RECONF2008-24, pp. 7-12, Sept. 2008. | |
| Paper # | RECONF2008-24 | |
| Date of Issue | 2008-09-18 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2008-24 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2008-09-25 - 2008-09-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okayama Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2008-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | JPEG Encode |
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| 1st Author's Name | Naomichi Furushima |
| 1st Author's Affiliation | Okayama University (Okayama Univ) |
| 2nd Author's Name | Nobuya Watanabe |
| 2nd Author's Affiliation | Okayama University (Okayama Univ) |
| 3rd Author's Name | Akira Nagoya |
| 3rd Author's Affiliation | Okayama University (Okayama Univ) |
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| Speaker | Author-1 |
| Date Time | 2008-09-25 13:30:00 |
| Presentation Time | 30 minutes |
| Registration for | RECONF |
| Paper # | RECONF2008-24 |
| Volume (vol) | vol.108 |
| Number (no) | no.220 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2008-09-18 (RECONF) |
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