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| Paper Abstract and Keywords | ||
| Presentation | 2008-07-25 13:00 Implementation of Block Cipher Camellia with a Configurable and Extensible Processor Kazuyoshi Matsuo, Koki Abe (UEC)  ISEC2008-45 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Camellia, a block cipher algorithm, has been implemented on a configurable and extensible processor to measure cycles and power consumption required for processing the algorithm when varying the configuration parameters and/or extending the instruction set of the processor. Results of optimizing configuration parameters revealed the reduction of processing cycles by approximately 10%. Extending the instruction set reduced processing cycles and total power consumption by 1/106 and 1/18, respectively. The extension has larger effect on reducing total power consumption for processing Camellia than AES. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Camellia / block cipher / configurable and extensible processor / power consumption / processing cycle / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 162, ISEC2008-45, pp. 75-80, July 2008. | |
| Paper # | ISEC2008-45 | |
| Date of Issue | 2008-07-18 (ISEC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ISEC2008-45 |
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| Conference Information | |
| Committee | ISEC SITE IPSJ-CSEC |
| Conference Date | 2008-07-24 - 2008-07-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Fukuoka Institute of System LSI Design Industry |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ISEC |
| Conference Code | 2008-07-ISEC-SITE-CSEC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Block Cipher Camellia with a Configurable and Extensible Processor |
| Sub Title (in English) | |
| Keyword(1) | Camellia |
| Keyword(2) | block cipher |
| Keyword(3) | configurable and extensible processor |
| Keyword(4) | power consumption |
| Keyword(5) | processing cycle |
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| Keyword(7) | |
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| 1st Author's Name | Kazuyoshi Matsuo |
| 1st Author's Affiliation | The University of Electro-Communications (UEC) |
| 2nd Author's Name | Koki Abe |
| 2nd Author's Affiliation | The University of Electro-Communications (UEC) |
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| Speaker | Author-1 |
| Date Time | 2008-07-25 13:00:00 |
| Presentation Time | 25 minutes |
| Registration for | ISEC |
| Paper # | ISEC2008-45 |
| Volume (vol) | vol.108 |
| Number (no) | no.162 |
| Page | pp.75-80 |
| #Pages | 6 |
| Date of Issue | 2008-07-18 (ISEC) |
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