IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-07-18 14:15
Realistic future trend of non-voltile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory -- feasibility study of BiCS type FeRAM and MRAM --
Shigeyoshi Watanabe, Koichi Sugano, Shouto Tamai (Shonan Institute of Tech.) SDM2008-145 ICD2008-55 Link to ES Tech. Rep. Archives: SDM2008-145 ICD2008-55
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
Keyword (in Japanese) (See Japanese page) 
(in English) / / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 139, SDM2008-145, pp. 97-102, July 2008.
Paper # SDM2008-145 
Date of Issue 2008-07-10 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2008-145 ICD2008-55 Link to ES Tech. Rep. Archives: SDM2008-145 ICD2008-55

Conference Information
Committee ICD SDM  
Conference Date 2008-07-17 - 2008-07-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2008-07-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Realistic future trend of non-voltile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory 
Sub Title (in English) feasibility study of BiCS type FeRAM and MRAM 
Keyword(1)  
Keyword(2)  
Keyword(3)  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shigeyoshi Watanabe  
1st Author's Affiliation Shonan Institute of Technology (Shonan Institute of Tech.)
2nd Author's Name Koichi Sugano  
2nd Author's Affiliation Shonan Institute of Technology (Shonan Institute of Tech.)
3rd Author's Name Shouto Tamai  
3rd Author's Affiliation Shonan Institute of Technology (Shonan Institute of Tech.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2008-07-18 14:15:00 
Presentation Time 25 
Registration for SDM 
Paper # IEICE-SDM2008-145,IEICE-ICD2008-55 
Volume (vol) IEICE-108 
Number (no) no.139(SDM), no.140(ICD) 
Page pp.97-102 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2008-07-10,IEICE-ICD-2008-07-10 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan