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| Presentation | 2008-07-18 09:50 A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support Koichi Nakayama, Ken-ichi Kawasaki, Tetsuyoshi Shiota, Atsuki Inoue (Fujitsu Lab.)  SDM2008-141 ICD2008-51 Link to ES Tech. Rep. Archives: SDM2008-141 ICD2008-51 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A sub-$\micro$s wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and separated power lines bypassing rush current to suppress power supply voltage fluctuations. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24$\micro$s, the supply voltage fluctuation was suppressed to 2.5mV. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | stand-by leakage / power gating / wake-up time / rush current noise / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 140, ICD2008-51, pp. 77-82, July 2008. | |
| Paper # | ICD2008-51 | |
| Date of Issue | 2008-07-10 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2008-141 ICD2008-51 Link to ES Tech. Rep. Archives: SDM2008-141 ICD2008-51 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2008-07-17 - 2008-07-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2008-07-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support |
| Sub Title (in English) | |
| Keyword(1) | stand-by leakage |
| Keyword(2) | power gating |
| Keyword(3) | wake-up time |
| Keyword(4) | rush current noise |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Koichi Nakayama |
| 1st Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Lab.) |
| 2nd Author's Name | Ken-ichi Kawasaki |
| 2nd Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Lab.) |
| 3rd Author's Name | Tetsuyoshi Shiota |
| 3rd Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Lab.) |
| 4th Author's Name | Atsuki Inoue |
| 4th Author's Affiliation | Fujitsu Laboratories Ltd. (Fujitsu Lab.) |
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| Speaker | 1 |
| Date Time | 2008-07-18 09:50:00 |
| Presentation Time | 25 |
| Registration for | ICD |
| Paper # | IEICE-SDM2008-141,IEICE-ICD2008-51 |
| Volume (vol) | IEICE-108 |
| Number (no) | no.139(SDM), no.140(ICD) |
| Page | pp.77-82 |
| #Pages | IEICE-6 |
| Date of Issue | IEICE-SDM-2008-07-10,IEICE-ICD-2008-07-10 |
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