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| Presentation | 2008-07-10 10:00 2-bit Arithmetic Logic Unit Utilizing Hexagonal BDD Architecture for Implemention of Nanoprocessor on GaAs Nanowire Network Hong-Quan Zhao (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST), Tamotsu Hashizume (Hokkaido Univ.)  ED2008-66 SDM2008-85 Link to ES Tech. Rep. Archives: ED2008-66 SDM2008-85 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | 2-bit arithmetic logic unit (ALU) utilizing the binary-decision diagram (BDD) logic architecture for nanoprocessor is fabricated on GaAs hexagonal nanowire networks with Schottky wrap gates (WPGs) and their operation is characterized. The ALU integrates 32 node devices and implements 4 instructions. They are fabricated by 3M or 16M nodes/cm2 fabrication processes. Fabricated ALU shows correct operations experimentally obtained in classical transport domain at room temperature. Supply voltage and input voltage swing dependences of the circuit operation are characterized. Discrete node devices are also investigated from viewpoint of integration, including path switching, threshold voltage variation and gate leakage current. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Arithmetic logic unit (ALU) / Nanowire network / Binary decision diagram (BDD) / Wrap gate (WPG) / GaAs / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 121, ED2008-66, pp. 139-144, July 2008. | |
| Paper # | ED2008-66 | |
| Date of Issue | 2008-07-02 (ED, SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ED2008-66 SDM2008-85 Link to ES Tech. Rep. Archives: ED2008-66 SDM2008-85 |
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| Conference Information | |
| Committee | SDM ED |
| Conference Date | 2008-07-09 - 2008-07-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kaderu２・７ |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices |
| Paper Information | |
| Registration To | ED |
| Conference Code | 2008-07-SDM-ED |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 2-bit Arithmetic Logic Unit Utilizing Hexagonal BDD Architecture for Implemention of Nanoprocessor on GaAs Nanowire Network |
| Sub Title (in English) | |
| Keyword(1) | Arithmetic logic unit (ALU) |
| Keyword(2) | Nanowire network |
| Keyword(3) | Binary decision diagram (BDD) |
| Keyword(4) | Wrap gate (WPG) |
| Keyword(5) | GaAs |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hong-Quan Zhao |
| 1st Author's Affiliation | Hokkaido University (Hokkaido Univ.) |
| 2nd Author's Name | Seiya Kasai |
| 2nd Author's Affiliation | Hokkaido UniversityJST (Hokkaido Univ./JST) |
| 3rd Author's Name | Tamotsu Hashizume |
| 3rd Author's Affiliation | Hokkaido University (Hokkaido Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-07-10 10:00:00 |
| Presentation Time | 15 minutes |
| Registration for | ED |
| Paper # | ED2008-66, SDM2008-85 |
| Volume (vol) | vol.108 |
| Number (no) | no.121(ED), no.122(SDM) |
| Page | pp.139-144 |
| #Pages | 6 |
| Date of Issue | 2008-07-02 (ED, SDM) |
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