Paper Abstract and Keywords |
Presentation |
2008-06-26 13:50
Evaluation of Dynamically Reconfigurable Processor in Implementing Sequential Execution of Image Processing Ryosuke Watanabe, Koki Abe (UEC) CAS2008-11 VLD2008-24 SIP2008-45 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, image applications are frequently executed using mobile devises, where executions with high speed at low cost are demanded.
Typically, in image applications, procedures with high complexity are executed sequentially.
In this study, we conducted an experiment to execute such an image application by a dynamically reconfigurable processor (DRP) and compared the processing speed with general purpose processors.
We took a sequential application of median and Laplacian filters as an example.
Results revealed that a DRP implementation executes 70 and 45 times faster than Celeron and Core2Duo processors, respectively.
We also discussed area, energy, and development costs when using DRP, and compared the costs with FPGA and ASIC.
When implementing image applications consisting of serial procedures, DRP is effective when the procedures are complex and available resources are limited. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Dynamically Reconfigurable Processor / Image Processing / Processing Speed / Development Cost / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 108, SIP2008-45, pp. 57-62, June 2008. |
Paper # |
SIP2008-45 |
Date of Issue |
2008-06-19 (CAS, VLD, SIP) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2008-11 VLD2008-24 SIP2008-45 |
Conference Information |
Committee |
VLD CAS SIP |
Conference Date |
2008-06-26 - 2008-06-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido Univ. |
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(See Japanese page) |
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Paper Information |
Registration To |
SIP |
Conference Code |
2008-06-VLD-CAS-SIP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Evaluation of Dynamically Reconfigurable Processor in Implementing Sequential Execution of Image Processing |
Sub Title (in English) |
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Keyword(1) |
Dynamically Reconfigurable Processor |
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Image Processing |
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Processing Speed |
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Development Cost |
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1st Author's Name |
Ryosuke Watanabe |
1st Author's Affiliation |
The University of Electro Communications (UEC) |
2nd Author's Name |
Koki Abe |
2nd Author's Affiliation |
The University of Electro Communications (UEC) |
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Speaker |
Author-1 |
Date Time |
2008-06-26 13:50:00 |
Presentation Time |
20 minutes |
Registration for |
SIP |
Paper # |
CAS2008-11, VLD2008-24, SIP2008-45 |
Volume (vol) |
vol.108 |
Number (no) |
no.104(CAS), no.106(VLD), no.108(SIP) |
Page |
pp.57-62 |
#Pages |
6 |
Date of Issue |
2008-06-19 (CAS, VLD, SIP) |
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