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| Presentation | 2008-05-13 10:30 An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) Link to ES Tech. Rep. Archives:  ICD2008-20 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which exploits whole program parallelism by analyzing hierarchical coarse grain task parallelism inside loops and subroutines, has been proposed and implemented in OSCAR automatic parallelizing compiler. This hierarchical coarse grain task parallel processing defines processor groups hierarchically and logically, and assigns hierarchical coarse grain tasks to each processor group. A light-weight and scalable barrier synchronization mechanism considering hierarchical processor grouping, which supports hierarchical coarse grain task parallel processing, is developed and implemented into RP2 multicore processor having eight SH4A cores with support by NEDO “Multicore Technology for Realtime Consumer Electronics”. This barrier mechanism is proposed and evaluated in this paper. The evaluation using AAC encoder program by 8 cores shows our barrier mechanism achieves 16% better performance than software barrier. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multicore Processor / Automatic Parallelizing Compiler / Barrier Synchronization Mechanism / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, pp. 19-24, May 2008. | |
| Paper # | ||
| Date of Issue | 2008-05-06 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2008-20 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC |
| Conference Date | 2008-05-13 - 2008-05-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | IPSJ-ARC |
| Conference Code | 2008-05-ICD-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping |
| Sub Title (in English) | |
| Keyword(1) | Multicore Processor |
| Keyword(2) | Automatic Parallelizing Compiler |
| Keyword(3) | Barrier Synchronization Mechanism |
| Keyword(4) | |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kaito Yamada |
| 1st Author's Affiliation | Hitachi, Ltd. (Hitachi) |
| 2nd Author's Name | Masayoshi Mase |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Jun Shirako |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Keiji Kimura |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Masayuki Ito |
| 5th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 6th Author's Name | Toshihiro Hattori |
| 6th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 7th Author's Name | Hiroyuki Mizuno |
| 7th Author's Affiliation | Hitachi, Ltd. (Hitachi) |
| 8th Author's Name | Kunio Uchiyama |
| 8th Author's Affiliation | Hitachi, Ltd. (Hitachi) |
| 9th Author's Name | Hironori Kasahara |
| 9th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-05-13 10:30:00 |
| Presentation Time | 30 minutes |
| Registration for | IPSJ-ARC |
| Paper # | ICD2008-20 |
| Volume (vol) | vol.108 |
| Number (no) | no.28 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2008-05-06 (ICD) |
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