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Paper Abstract and Keywords
Presentation 2008-05-09 11:40
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) VLD2008-9
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shrinking process geometries, coupling power between neighboring bus lines has enlarged. The coupling power depends on not only signal transition type but also the relative signal transition time difference. For conventional dynamic power estimation, deterministic models of the time difference are assumed. We deal with nondeterministic models such as process variations, because these variations cause the input arrival time variations. As a result, the arrival time variations increase power estimation error. In our analysis and experiments, following results are presented. 1) When there are both the arrival time variations and unbalanced occurrence probability of
similarly switching compared with oppositely switching, the power stimation error is large. 2) Bus coding, which reduces similarly and/or oppositely switching, has beneficial effects on both power reduction and the error reduction.
Keyword (in Japanese) (See Japanese page) 
(in English) input arrival time variation / on-chip bus / coupling power / power estiamtion / low power bus coding / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 23, VLD2008-9, pp. 13-18, May 2008.
Paper # VLD2008-9 
Date of Issue 2008-05-02 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-9

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2008-05-08 - 2008-05-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2008-05-VLD-SLDM 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption 
Sub Title (in English)  
Keyword(1) input arrival time variation  
Keyword(2) on-chip bus  
Keyword(3) coupling power  
Keyword(4) power estiamtion  
Keyword(5) low power bus coding  
1st Author's Name Masanori Muroyama  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Tohru Ishihara  
2nd Author's Affiliation Kyushu University (Kyushu Univ.)
3rd Author's Name Hiroto Yasuura  
3rd Author's Affiliation Kyushu University (Kyushu Univ.)
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Date Time 2008-05-09 11:40:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-9 
Volume (vol) IEICE-108 
Number (no) no.23 
Page pp.13-18 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2008-05-02 

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