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| Presentation | 2008-05-09 13:30 Fine-Grained Power Gating Based on the Controlling Value of Logic Gates Lei Chen (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.)  VLD2008-10 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating approach based on the controlling value of logic gates is proposed for leakage power reduction. In the method, sleep signals of the power-gated blocks are extracted based on the probability of the controlling value of logic gates without any extra control logic. A basic algorithm and a probability-based heuristic algorithm have been developed to implement this method. The steady maximum delay constraint has also been introduced to handle the delay overhead. Experiments on the ISCAS'85 benchmarks show the effectiveness of our algorithms and the effect on the extra delay. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Power gating / Multi-threshold CMOS (MTCMOS) technology / BDD / Controlling value / Leakage power reduction / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 23, VLD2008-10, pp. 19-24, May 2008. | |
| Paper # | VLD2008-10 | |
| Date of Issue | 2008-05-02 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2008-10 |
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| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2008-05-08 - 2008-05-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kobe Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-05-VLD-SLDM |
| Language | English (Japanese title is available) |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fine-Grained Power Gating Based on the Controlling Value of Logic Gates |
| Sub Title (in English) | |
| Keyword(1) | Power gating |
| Keyword(2) | Multi-threshold CMOS (MTCMOS) technology |
| Keyword(3) | BDD |
| Keyword(4) | Controlling value |
| Keyword(5) | Leakage power reduction |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Lei Chen |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Takashi Horiyama |
| 2nd Author's Affiliation | Saitama University (Saitama Univ.) |
| 3rd Author's Name | Yuichi Nakamura |
| 3rd Author's Affiliation | NEC Corporation (NEC) |
| 4th Author's Name | Shinji Kimura |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-05-09 13:30:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2008-10 |
| Volume (vol) | vol.108 |
| Number (no) | no.23 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2008-05-02 (VLD) |
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