講演抄録/キーワード |
講演名 |
2008-05-09 13:30
制御値に基づく細粒度パワーゲーティング手法 ○陳 磊(早大)・堀山貴史(埼玉大)・中村裕一(NEC)・木村晋二(早大) VLD2008-10 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating approach based on the controlling value of logic gates is proposed for leakage power reduction. In the method, sleep signals of the power-gated blocks are extracted based on the probability of the controlling value of logic gates without any extra control logic. A basic algorithm and a probability-based heuristic algorithm have been developed to implement this method. The steady maximum delay constraint has also been introduced to handle the delay overhead. Experiments on the ISCAS'85 benchmarks show the effectiveness of our algorithms and the effect on the extra delay. |
キーワード |
(和) |
/ / / / / / / |
(英) |
Power gating / Multi-threshold CMOS (MTCMOS) technology / BDD / Controlling value / Leakage power reduction / / / |
文献情報 |
信学技報, vol. 108, no. 23, VLD2008-10, pp. 19-24, 2008年5月. |
資料番号 |
VLD2008-10 |
発行日 |
2008-05-02 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
VLD2008-10 |