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Paper Abstract and Keywords
Presentation 2008-05-09 15:00
On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints
Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-13
Abstract (in Japanese) (See Japanese page) 
(in English) Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded
system at a cheap cost within short development time. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional design flow, while chip area, performance, and power consumption have been. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and SEU vulnerability constraints. We build an MIP model for minimizing chip area
of a heterogeneous multiprocessor system under the constraints. Experimental results show that our design paradigm have achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.
Keyword (in Japanese) (See Japanese page) 
(in English) SEU / Soft Error / Real-Time / SEU Vulnerability / Heterogeneous Multiprocessor / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 23, VLD2008-13, pp. 37-42, May 2008.
Paper # VLD2008-13 
Date of Issue 2008-05-02 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2008-05-08 - 2008-05-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2008-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints 
Sub Title (in English)  
Keyword(1) SEU  
Keyword(2) Soft Error  
Keyword(3) Real-Time  
Keyword(4) SEU Vulnerability  
Keyword(5) Heterogeneous Multiprocessor  
1st Author's Name Makoto Sugihara  
1st Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech./JST-CREST)
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Date Time 2008-05-09 15:00:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2008-13 
Volume (vol) IEICE-108 
Number (no) no.23 
Page pp.37-42 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2008-05-02 

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