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Paper Abstract and Keywords
Presentation 2008-03-27 08:45
An Adaptive Multi-Performance Processor and its Evaluation
Seiichiro Yamaguchi, Yuichiro Oyama (Kyushu Univ.), Yuji Kunitake (Kyushu Inst. of Tech.), Tadayuki Matsumura, Yuriko Ishitobi, Masaki Yamaguchi, Donghoon Lee, Yusuke Kaneda (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst. of Tech.), Masanori Muroyama, Tohru Ishihara, Toshinori Sato (Kyushu Univ.) DC2007-84 CPSY2007-80
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor core consists of multiple PE (processing element) cores and a scalable set-associative cache memory. The major advantage over the DVS processors is a small overhead for changing its operating speeds. Our processor can change its speeds in 1u second while conventional DVS processors need hundreds of microseconds for the performance transition.
Keyword (in Japanese) (See Japanese page) 
(in English) microprocessor / low power design / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 559, DC2007-84, pp. 1-6, March 2008.
Paper # DC2007-84 
Date of Issue 2008-03-20 (DC, CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB  
Conference Date 2008-03-27 - 2008-03-28 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2008-03-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Adaptive Multi-Performance Processor and its Evaluation 
Sub Title (in English)  
Keyword(1) microprocessor  
Keyword(2) low power design  
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1st Author's Name Seiichiro Yamaguchi  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Yuichiro Oyama  
2nd Author's Affiliation Kyushu University (Kyushu Univ.)
3rd Author's Name Yuji Kunitake  
3rd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
4th Author's Name Tadayuki Matsumura  
4th Author's Affiliation Kyushu University (Kyushu Univ.)
5th Author's Name Yuriko Ishitobi  
5th Author's Affiliation Kyushu University (Kyushu Univ.)
6th Author's Name Masaki Yamaguchi  
6th Author's Affiliation Kyushu University (Kyushu Univ.)
7th Author's Name Donghoon Lee  
7th Author's Affiliation Kyushu University (Kyushu Univ.)
8th Author's Name Yusuke Kaneda  
8th Author's Affiliation Kyushu University (Kyushu Univ.)
9th Author's Name Toshimasa Funaki  
9th Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
10th Author's Name Masanori Muroyama  
10th Author's Affiliation Kyushu University (Kyushu Univ.)
11th Author's Name Tohru Ishihara  
11th Author's Affiliation Kyushu University (Kyushu Univ.)
12th Author's Name Toshinori Sato  
12th Author's Affiliation Kyushu University (Kyushu Univ.)
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Speaker
Date Time 2008-03-27 08:45:00 
Presentation Time 20 
Registration for DC 
Paper # IEICE-DC2007-84,IEICE-CPSY2007-80 
Volume (vol) IEICE-107 
Number (no) no.559(DC), no.558(CPSY) 
Page pp.1-6 
#Pages IEICE-6 
Date of Issue IEICE-DC-2008-03-20,IEICE-CPSY-2008-03-20 


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