Paper Abstract and Keywords |
Presentation |
2008-03-27 08:45
An Adaptive Multi-Performance Processor and its Evaluation Seiichiro Yamaguchi, Yuichiro Oyama (Kyushu Univ.), Yuji Kunitake (Kyushu Inst. of Tech.), Tadayuki Matsumura, Yuriko Ishitobi, Masaki Yamaguchi, Donghoon Lee, Yusuke Kaneda (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst. of Tech.), Masanori Muroyama, Tohru Ishihara, Toshinori Sato (Kyushu Univ.) DC2007-84 CPSY2007-80 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor core consists of multiple PE (processing element) cores and a scalable set-associative cache memory. The major advantage over the DVS processors is a small overhead for changing its operating speeds. Our processor can change its speeds in 1u second while conventional DVS processors need hundreds of microseconds for the performance transition. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
microprocessor / low power design / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 559, DC2007-84, pp. 1-6, March 2008. |
Paper # |
DC2007-84 |
Date of Issue |
2008-03-20 (DC, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
DC2007-84 CPSY2007-80 |
|