Paper Abstract and Keywords |
Presentation |
2008-03-13 11:15
An Architecture of Dynamically Reconfigurable Systolic Array Toshiyuki Ishimura, Akinori Kanasugi (TDU) SIS2007-70 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The Dynamically Reconfigurable Device which has high-speed performance of ASIC, flexibility of FPGA and high area efficiency is paid to attention recently. In this paper, we propose an element-block (DRSAB) which allows dynamic reconfiguration of systolic array. The array is constructed with simple PEs operating matrix calculation, and it is adapted to different size problems. In addition, the array can manage parallel processing by partially reconstructing the computing resources. The effectiveness of proposed DRSAB is confirmed with simulation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Reconfigurable / Systolic Array / Processing Element / Digital signal processing / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 547, SIS2007-70, pp. 11-16, March 2008. |
Paper # |
SIS2007-70 |
Date of Issue |
2008-03-06 (SIS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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SIS2007-70 |
Conference Information |
Committee |
SIS |
Conference Date |
2008-03-13 - 2008-03-14 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Musashi Institute of Technology(Setagaya) |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
SIS |
Conference Code |
2008-03-SIS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Architecture of Dynamically Reconfigurable Systolic Array |
Sub Title (in English) |
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Reconfigurable |
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Systolic Array |
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Processing Element |
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Digital signal processing |
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1st Author's Name |
Toshiyuki Ishimura |
1st Author's Affiliation |
Tokyo Denki University (TDU) |
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Akinori Kanasugi |
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Tokyo Denki University (TDU) |
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Speaker |
Author-1 |
Date Time |
2008-03-13 11:15:00 |
Presentation Time |
20 minutes |
Registration for |
SIS |
Paper # |
SIS2007-70 |
Volume (vol) |
vol.107 |
Number (no) |
no.547 |
Page |
pp.11-16 |
#Pages |
6 |
Date of Issue |
2008-03-06 (SIS) |
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