Paper Abstract and Keywords |
Presentation |
2008-03-07 13:00
[Poster Presentation]
Architecture of 1Gbps IPsec Accelerator Kazuya Asano, Tomokazu Aoki, Teruhiko Nagatomo, Taku Sugawara, Taul Katayama, Junichi Hashida, Norio Abe, Satoru Okamoto (FLS), Yukinori Abe (Fujitsu) CAS2007-137 SIP2007-212 CS2007-102 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have developed a 1Gbps IPsec accelerator and show its architecture in this paper. The IPsec accelerator can process IPsec at wire-rate full-duplex 1Gbps throughput across all packet sizes thanks to a parallel-pipeline architecture for each of encryption and decryption. It operates only at 150MHz, which enables us to use low power process and resulted in high performance / Watt. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
1Gbps / IPsec / accelerator / low power / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 531, CS2007-102, pp. 67-68, March 2008. |
Paper # |
CS2007-102 |
Date of Issue |
2008-02-29 (CAS, SIP, CS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CAS2007-137 SIP2007-212 CS2007-102 |
Conference Information |
Committee |
CS SIP CAS |
Conference Date |
2008-03-06 - 2008-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Yamaguchi University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Network processors, signal processing for communications, wireless LAN/PAN, etc. |
Paper Information |
Registration To |
CS |
Conference Code |
2008-03-CS-SIP-CAS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Architecture of 1Gbps IPsec Accelerator |
Sub Title (in English) |
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Keyword(1) |
1Gbps |
Keyword(2) |
IPsec |
Keyword(3) |
accelerator |
Keyword(4) |
low power |
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1st Author's Name |
Kazuya Asano |
1st Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
2nd Author's Name |
Tomokazu Aoki |
2nd Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
3rd Author's Name |
Teruhiko Nagatomo |
3rd Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
4th Author's Name |
Taku Sugawara |
4th Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
5th Author's Name |
Taul Katayama |
5th Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
6th Author's Name |
Junichi Hashida |
6th Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
7th Author's Name |
Norio Abe |
7th Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
8th Author's Name |
Satoru Okamoto |
8th Author's Affiliation |
Fujitsu LSI Solution Limited (FLS) |
9th Author's Name |
Yukinori Abe |
9th Author's Affiliation |
Fujitsu Lmited (Fujitsu) |
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Speaker |
Author-1 |
Date Time |
2008-03-07 13:00:00 |
Presentation Time |
60 minutes |
Registration for |
CS |
Paper # |
CAS2007-137, SIP2007-212, CS2007-102 |
Volume (vol) |
vol.107 |
Number (no) |
no.527(CAS), no.529(SIP), no.531(CS) |
Page |
pp.67-68 |
#Pages |
2 |
Date of Issue |
2008-02-29 (CAS, SIP, CS) |
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