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| Presentation | 2008-03-07 13:50 A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)  VLD2007-163 ICD2007-186 Link to ES Tech. Rep. Archives: ICD2007-186 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper shows the principle and architecture of a low-cost speed and yield enhancement method using enbedded delay detectors on FPGAs. we apply critical path reconfiguration to utilize random variations for performance enhancement. We have to know which path is faster on the critical path reconfiguration, but the cost of measurement by path-delay measurement method is very large. In order to search for faster paths with much lower cost, we propose measurement method using delay detectors. Computing measurement cost by delay detectors can be treated as an edge-coloring probelem. The cost is equal edge-color number $k$. The order of $k$ is derived from the upper and lower bound of the measurment cost. $k$ is independent of the circuit size and turned out to be constant. The computation time for this algorithm is $O(n)$ where $n$ is the number of CLBs in the critical path candidates. By implementing and applying this algorithm to a set of benchmark circuits we verified that the measurment cost is close to the lower bound. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / Variation-aware / Yield Enhancement / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 508, VLD2007-163, pp. 41-46, March 2008. | |
| Paper # | VLD2007-163 | |
| Date of Issue | 2008-02-29 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-163 ICD2007-186 Link to ES Tech. Rep. Archives: ICD2007-186 |
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| Conference Information | |
| Committee | VLD ICD |
| Conference Date | 2008-03-05 - 2008-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | TiRuRu |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-03-VLD-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Variation-aware |
| Keyword(3) | Yield Enhancement |
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| 1st Author's Name | Yohei Kume |
| 1st Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 2nd Author's Name | Yuuri Sugihara |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Ngo Cam Lai |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 4th Author's Name | Kazutoshi Kobayashi |
| 4th Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 5th Author's Name | Hidetoshi Onodera |
| 5th Author's Affiliation | Kyoto University (Kyoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-03-07 13:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-163, ICD2007-186 |
| Volume (vol) | vol.107 |
| Number (no) | no.508(VLD), no.511(ICD) |
| Page | pp.41-46 |
| #Pages | 6 |
| Date of Issue | 2008-02-29 (VLD, ICD) |
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