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| Presentation | 2008-03-07 13:00 [Poster Presentation] Code Optimization Method for Bypass Network Architechture by Evalation of DFG Toshihiro Shoji, Jin Tian, Takefumi Miyoshi, Nobuhiko Sugino (Tokyo Tech．)  CAS2007-139 SIP2007-214 CS2007-104 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | For a bypass interconnected processor architecture, a heuristic code optimization method is proposed. In total power consumption of a processor, power consumption at register access account for relatively higher percentage. For reducing this rate, there have been proposed a bypass interconnected architecture, which can replace register accesses by data forwarding latch accesses. In order to use bypass effectively, however, computational order of instruction codes should be rearranged. In this article, data dependencies in a given program is analyzed by the corresponding data flow graph, and a novel code rescheduling method is proposed. The proposed method is applied to an example program, and comparison of the resultant code with codes derived by the existing code optimization method based on computational order exchange, shows its effectiveness. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Scheduling / Low-power / Bypass Network Architecture / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 527, CAS2007-139, pp. 75-78, March 2008. | |
| Paper # | CAS2007-139 | |
| Date of Issue | 2008-02-29 (CAS, SIP, CS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2007-139 SIP2007-214 CS2007-104 |
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| Conference Information | |
| Committee | CS SIP CAS |
| Conference Date | 2008-03-06 - 2008-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Yamaguchi University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Network processors, signal processing for communications, wireless LAN/PAN, etc. |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2008-03-CS-SIP-CAS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Code Optimization Method for Bypass Network Architechture by Evalation of DFG |
| Sub Title (in English) | |
| Keyword(1) | Scheduling |
| Keyword(2) | Low-power |
| Keyword(3) | Bypass Network Architecture |
| Keyword(4) | |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Toshihiro Shoji |
| 1st Author's Affiliation | Tokyo Institute Of Technology (Tokyo Tech．) |
| 2nd Author's Name | Jin Tian |
| 2nd Author's Affiliation | Tokyo Institute Of Technology (Tokyo Tech．) |
| 3rd Author's Name | Takefumi Miyoshi |
| 3rd Author's Affiliation | Tokyo Institute Of Technology (Tokyo Tech．) |
| 4th Author's Name | Nobuhiko Sugino |
| 4th Author's Affiliation | Tokyo Institute Of Technology (Tokyo Tech．) |
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| Speaker | Author-1 |
| Date Time | 2008-03-07 13:00:00 |
| Presentation Time | 60 minutes |
| Registration for | CAS |
| Paper # | CAS2007-139, SIP2007-214, CS2007-104 |
| Volume (vol) | vol.107 |
| Number (no) | no.527(CAS), no.529(SIP), no.531(CS) |
| Page | pp.75-78 |
| #Pages | 4 |
| Date of Issue | 2008-02-29 (CAS, SIP, CS) |
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