IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-03-05 15:45
MOS Analog Module Generation
Akio Fujii, Takehiko Matsuo, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2007-143 ICD2007-166 Link to ES Tech. Rep. Archives: ICD2007-166
Abstract (in Japanese) (See Japanese page) 
(in English) This paper addresses the module layout configuration issue of MOS analog LSI. We notice that the key characteristic of this issue is that the data scale is not so large, but it needs a lot of constrains and a high layout quality.
Then, we formulate the routing problem as mixed integer linear problem (MILP). Hence, we successfully obtain a disjoint routing for multiple nets
by introducing the formulation based on network flow.
Furthermore, the compaction problem is combined into the routing problem based on MILP, so that we attain an exact optimum layout for the module configulation.
Keyword (in Japanese) (See Japanese page) 
(in English) Analog Module Configuration / Routing / Mixed Integer Linear Programming / / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 506, VLD2007-143, pp. 37-42, March 2008.
Paper # VLD2007-143 
Date of Issue 2008-02-27 (VLD, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-143 ICD2007-166 Link to ES Tech. Rep. Archives: ICD2007-166

Conference Information
Committee VLD ICD  
Conference Date 2008-03-05 - 2008-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) TiRuRu 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System-on-silicon design techniques and related VLSs 
Paper Information
Registration To VLD 
Conference Code 2008-03-VLD-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) MOS Analog Module Generation 
Sub Title (in English)  
Keyword(1) Analog Module Configuration  
Keyword(2) Routing  
Keyword(3) Mixed Integer Linear Programming  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Akio Fujii  
1st Author's Affiliation University of Kitakyushu (Univ. of Kitakyushu)
2nd Author's Name Takehiko Matsuo  
2nd Author's Affiliation University of Kitakyushu (Univ. of Kitakyushu)
3rd Author's Name Toru Fujimura  
3rd Author's Affiliation University of Kitakyushu (Univ. of Kitakyushu)
4th Author's Name Bo Yang  
4th Author's Affiliation University of Kitakyushu (Univ. of Kitakyushu)
5th Author's Name Shigetoshi Nakatake  
5th Author's Affiliation University of Kitakyushu (Univ. of Kitakyushu)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2008-03-05 15:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-143, ICD2007-166 
Volume (vol) vol.107 
Number (no) no.506(VLD), no.509(ICD) 
Page pp.37-42 
#Pages
Date of Issue 2008-02-27 (VLD, ICD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan