Paper Abstract and Keywords |
Presentation |
2008-01-31 10:50
Analysis on 4RTD Logic Circuits Tomohiko Ebata, Hiroki Okuyama, Takao Waho (Sophia Univ.) ED2007-248 SDM2007-259 Link to ES Tech. Rep. Archives: ED2007-248 SDM2007-259 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
4RTD logic operation has been analyzed based on a circuit model, circuit simulation, and experiment. First, equations describing the biasing clock current that is required to obtain OR/AND and NOR/NAND logic operation are derived. Then, design principle to increase the operation margin in terms of the clock current is presented. Increasing the input current is most effective for that purpose. It is also found that the OR/AND circuit has a wider margin than the NOR/NAND circuit. These predictions have been proved by the circuit measurement. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
resonant-tunneling diode / RTD / logic circuit / circuit simulation / experiment / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 473, ED2007-248, pp. 57-62, Jan. 2008. |
Paper # |
ED2007-248 |
Date of Issue |
2008-01-23 (ED, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ED2007-248 SDM2007-259 Link to ES Tech. Rep. Archives: ED2007-248 SDM2007-259 |
Conference Information |
Committee |
ED SDM |
Conference Date |
2008-01-30 - 2008-01-31 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ED |
Conference Code |
2008-01-ED-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Analysis on 4RTD Logic Circuits |
Sub Title (in English) |
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Keyword(1) |
resonant-tunneling diode |
Keyword(2) |
RTD |
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logic circuit |
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circuit simulation |
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experiment |
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1st Author's Name |
Tomohiko Ebata |
1st Author's Affiliation |
Sophia University (Sophia Univ.) |
2nd Author's Name |
Hiroki Okuyama |
2nd Author's Affiliation |
Sophia University (Sophia Univ.) |
3rd Author's Name |
Takao Waho |
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Sophia University (Sophia Univ.) |
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Speaker |
Author-1 |
Date Time |
2008-01-31 10:50:00 |
Presentation Time |
25 minutes |
Registration for |
ED |
Paper # |
ED2007-248, SDM2007-259 |
Volume (vol) |
vol.107 |
Number (no) |
no.473(ED), no.474(SDM) |
Page |
pp.57-62 |
#Pages |
6 |
Date of Issue |
2008-01-23 (ED, SDM) |
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