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| Presentation | 2008-01-17 17:40 C to HDL compiler for rapid HW-SW co-simulation models Yasuhiro Ito, Yutaka Sugawara, Kei Hiraki (Tokyo Univ.)  VLD2007-136 CPSY2007-79 RECONF2007-82 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The importance of verification for embedded systems increases as the scale of circuit and complexity of software increase, and the time for verification step also increases in development period. The verification environments should have the following two aspects: One is high-speed verification with cycle level accuracy. The other is to reduce man-hour by generating both the verification model and RTL from the same code. There is a proposed approach for high speed verification , which constructs hardware models with callbacks and calls registered callback functions after 0 or more delays reacting on change of the trigger signal. This approach have higher verification speed compared to existing approaches such as SystemC. However, it cannot generate RTL, thus it requires more man-hour for constructing verification model and RTL separately. We implemented a code converter for generating Verilog code from callback functions described in C. It is aimed to achieve both high verification speed and the RTL generative capacity. We implemented a SoC for evaluation by using both the callback-based verification model and Verilog. We measured the verification speed and the scale of RTL of both methods. With our method, the verification speed is four times faster than that of Verilog, with equal clock frequency and circuit scale. We show that the verification speed of our method was twenty four times faster than Verilog. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Verification / Embedded / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 417, CPSY2007-79, pp. 107-112, Jan. 2008. | |
| Paper # | CPSY2007-79 | |
| Date of Issue | 2008-01-10 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-136 CPSY2007-79 RECONF2007-82 |
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| Conference Information | |
| Committee | RECONF CPSY VLD IPSJ-SLDM |
| Conference Date | 2008-01-16 - 2008-01-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2008-01-RECONF-CPSY-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | C to HDL compiler for rapid HW-SW co-simulation models |
| Sub Title (in English) | |
| Keyword(1) | Verification |
| Keyword(2) | Embedded |
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| 1st Author's Name | Yasuhiro Ito |
| 1st Author's Affiliation | The University of Tokyo (Tokyo Univ.) |
| 2nd Author's Name | Yutaka Sugawara |
| 2nd Author's Affiliation | The University of Tokyo (Tokyo Univ.) |
| 3rd Author's Name | Kei Hiraki |
| 3rd Author's Affiliation | The University of Tokyo (Tokyo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-01-17 17:40:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | VLD2007-136, CPSY2007-79, RECONF2007-82 |
| Volume (vol) | vol.107 |
| Number (no) | no.415(VLD), no.417(CPSY), no.419(RECONF) |
| Page | pp.107-112 |
| #Pages | 6 |
| Date of Issue | 2008-01-10 (VLD, CPSY, RECONF) |
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