Paper Abstract and Keywords |
Presentation |
2008-01-17 09:40
Scheduling and Memory Binding in High Level Synthesis for FPGAs Yuki Sagawa, Tsuyoshi Sadakata, Yusuke Matsunaga (Kyusyu Univ.) VLD2007-120 CPSY2007-63 RECONF2007-66 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In High Level Synthesis for FPGAs,arrays in behavioral description may be bound to the same memory block since the number of memory block is fixed for FPGAs. The number of access to such arrays at one step is limited to the number of memory port. If arrays that are accessed frequently are bound to the same memory block,array accessess will conflict with each other and the conflict will affect the number of steps. Therefore, memory binding and scheduling should be considered simultaneously. In this paper,we propose a heuristic algorithm that deals with memory binding and scheduling simultaneously under the memory size,the number of memory,and the number of memory port constraints subject to minimize the sum of maximum step for all Data Flow Graphs. Experimental results show that the proposed algorithm can find as a good solution as the approach using Simulated Annealing in many cases. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-Level Synthesis / Memory Binding / Scheduling / FPGA / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 415, VLD2007-120, pp. 13-18, Jan. 2008. |
Paper # |
VLD2007-120 |
Date of Issue |
2008-01-10 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2007-120 CPSY2007-63 RECONF2007-66 |
Conference Information |
Committee |
RECONF CPSY VLD IPSJ-SLDM |
Conference Date |
2008-01-16 - 2008-01-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2008-01-RECONF-CPSY-VLD-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Scheduling and Memory Binding in High Level Synthesis for FPGAs |
Sub Title (in English) |
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Keyword(1) |
High-Level Synthesis |
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Memory Binding |
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Scheduling |
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FPGA |
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1st Author's Name |
Yuki Sagawa |
1st Author's Affiliation |
Kyusyu University (Kyusyu Univ.) |
2nd Author's Name |
Tsuyoshi Sadakata |
2nd Author's Affiliation |
Kyusyu University (Kyusyu Univ.) |
3rd Author's Name |
Yusuke Matsunaga |
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Kyusyu University (Kyusyu Univ.) |
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Speaker |
Author-1 |
Date Time |
2008-01-17 09:40:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2007-120, CPSY2007-63, RECONF2007-66 |
Volume (vol) |
vol.107 |
Number (no) |
no.415(VLD), no.417(CPSY), no.419(RECONF) |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2008-01-10 (VLD, CPSY, RECONF) |
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