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Paper Abstract and Keywords
Presentation 2008-01-16 14:10
An optimization method of DMA transfer for the SRC-6 reconfigurable machine
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2007-109 CPSY2007-52 RECONF2007-55
Abstract (in Japanese) (See Japanese page) 
(in English) DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. To mitigate this problem, the DMA transfer of SRC-6 supports streaming processing with a on-board memory interleave. However, as a preprocessing of the interleave, the CPU must reorder the data for applications with severe FPGA resource constraints. This paper empirically evaluates this overhead to reveal the trade-off point. The results show that the speedup is achieved by interleaved streaming DMA when FPGAs treat 150\,KB or lower of data per stream.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / DMA transfer / interleave / latency hiding / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 418, RECONF2007-55, pp. 25-30, Jan. 2008.
Paper # RECONF2007-55 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-109 CPSY2007-52 RECONF2007-55

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An optimization method of DMA transfer for the SRC-6 reconfigurable machine 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) DMA transfer  
Keyword(3) interleave  
Keyword(4) latency hiding  
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1st Author's Name Sayaka Shida  
1st Author's Affiliation Nagasaki University (Nagasaki Univ.)
2nd Author's Name Yuichiro Shibata  
2nd Author's Affiliation Nagasaki University (Nagasaki Univ.)
3rd Author's Name Kiyoshi Oguri  
3rd Author's Affiliation Nagasaki University (Nagasaki Univ.)
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Speaker Author-1 
Date Time 2008-01-16 14:10:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2007-109, CPSY2007-52, RECONF2007-55 
Volume (vol) vol.107 
Number (no) no.414(VLD), no.416(CPSY), no.418(RECONF) 
Page pp.25-30 
#Pages
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 


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