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| Presentation | 2008-01-16 15:10 Development of verification and power estimation methodology for circuits with Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.)  VLD2007-111 CPSY2007-54 RECONF2007-57 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | When applying Run-Time Power Gating (RTPG) to a design，logic verification is one of the major problems．Gate-level simulation cannot be carried out in the conventional verification environment because logic netlist includes power switch cells．In this paper，we propose logic modeling for a power switch and simulation methodology for power-gated circuits．In addition，we present about power estimation technique based on the proposed simulation methodology and the novel macro-modeling．Evaluation at ALU with RTPG showed that the accuracy of the estimated power was within 10% against the transistor-level simulation． | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | MTCMOS circuits / Power Gating / Power Dissipation / Development of verification / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 414, VLD2007-111, pp. 37-42, Jan. 2008. | |
| Paper # | VLD2007-111 | |
| Date of Issue | 2008-01-09 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-111 CPSY2007-54 RECONF2007-57 |
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| Conference Information | |
| Committee | RECONF CPSY VLD IPSJ-SLDM |
| Conference Date | 2008-01-16 - 2008-01-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of verification and power estimation methodology for circuits with Run Time Power Gating |
| Sub Title (in English) | |
| Keyword(1) | MTCMOS circuits |
| Keyword(2) | Power Gating |
| Keyword(3) | Power Dissipation |
| Keyword(4) | Development of verification |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Mitsutaka Nakata |
| 1st Author's Affiliation | Shibaura Institute of Technology (S.I.T.) |
| 2nd Author's Name | Toshiaki Shirai |
| 2nd Author's Affiliation | Shibaura Institute of Technology (S.I.T.) |
| 3rd Author's Name | Toshihiro Kashima |
| 3rd Author's Affiliation | Shibaura Institute of Technology (S.I.T.) |
| 4th Author's Name | Seidai Takeda |
| 4th Author's Affiliation | Shibaura Institute of Technology (S.I.T.) |
| 5th Author's Name | Kimiyoshi Usami |
| 5th Author's Affiliation | Shibaura Institute of Technology (S.I.T.) |
| 6th Author's Name | Naomi Seki |
| 6th Author's Affiliation | Keio University (Keio Univ.) |
| 7th Author's Name | Yohei Hasegawa |
| 7th Author's Affiliation | Keio University (Keio Univ.) |
| 8th Author's Name | Hideharu Amano |
| 8th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-01-16 15:10:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-111, CPSY2007-54, RECONF2007-57 |
| Volume (vol) | vol.107 |
| Number (no) | no.414(VLD), no.416(CPSY), no.418(RECONF) |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2008-01-09 (VLD, CPSY, RECONF) |
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