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Paper Abstract and Keywords
Presentation 2007-12-14 17:00
Neural Network of Device Level using Poly-Si TFT
Ryo Onodera, Tomohiro Kasakawa, Hiroki Kojima, Mutsumi Kimura (Ryukoku Univ.), Hiroyuki Hara, Satoshi Inoue (Seiko Epson Corp.) SDM2007-235 Link to ES Tech. Rep. Archives: SDM2007-235
Abstract (in Japanese) (See Japanese page) 
(in English) We have developed a neural network of device level using TFT. Extreamly simplified circuit configulation is achieved using characteristic variation of TFT, and learing behavior is confirmed. This work will make it possible to fabricate inexpensive and highly-integrated neural network on large substrate.
Keyword Poly-Si TFT, neural network, learning
Keyword (in Japanese) (See Japanese page) 
(in English) Poly-Si TFT / neural network / learning / / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 388, SDM2007-235, pp. 55-58, Dec. 2007.
Paper # SDM2007-235 
Date of Issue 2007-12-07 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-235 Link to ES Tech. Rep. Archives: SDM2007-235

Conference Information
Committee SDM  
Conference Date 2007-12-14 - 2007-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Nara Institute Science and Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Silicon related material, process and device 
Paper Information
Registration To SDM 
Conference Code 2007-12-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Neural Network of Device Level using Poly-Si TFT 
Sub Title (in English)  
Keyword(1) Poly-Si TFT  
Keyword(2) neural network  
Keyword(3) learning  
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1st Author's Name Ryo Onodera  
1st Author's Affiliation Ryukoku University (Ryukoku Univ.)
2nd Author's Name Tomohiro Kasakawa  
2nd Author's Affiliation Ryukoku University (Ryukoku Univ.)
3rd Author's Name Hiroki Kojima  
3rd Author's Affiliation Ryukoku University (Ryukoku Univ.)
4th Author's Name Mutsumi Kimura  
4th Author's Affiliation Ryukoku University (Ryukoku Univ.)
5th Author's Name Hiroyuki Hara  
5th Author's Affiliation Seiko Epson Corporation (Seiko Epson Corp.)
6th Author's Name Satoshi Inoue  
6th Author's Affiliation Seiko Epson Corporation (Seiko Epson Corp.)
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Speaker
Date Time 2007-12-14 17:00:00 
Presentation Time 20 
Registration for SDM 
Paper # IEICE-SDM2007-235 
Volume (vol) IEICE-107 
Number (no) no.388 
Page pp.55-58 
#Pages IEICE-4 
Date of Issue IEICE-SDM-2007-12-07 


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