Paper Abstract and Keywords |
Presentation |
2007-12-14 14:40
A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 Link to ES Tech. Rep. Archives: ICD2007-138 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) architecture. The MX-SoC has three MX-Cores, Host-CPU, and I/O peripheral modules. An unit MX-Core is a massively parallel (1024) flexible SIMD processor based on the matrix architecture. The MX-SoC, which can perform the image processing of CCD camera, is implemented on 90nm Low Power CMOS process technology and can operate at 162MHz under the worst condition. A novel parallel pixel data processing algorism, and multi task execution suitable for multi MX-Core processing can achieve 30 Frame/sec image processing. This performance is 30 times faster than general purpose CPU solution. The MX-SoC with multi MX-Core architecture can realize the software solution of real time image processing application field. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
massively parallel processing / SIMD / processor / image processing / SoC / multi processor / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 382, ICD2007-138, pp. 107-111, Dec. 2007. |
Paper # |
ICD2007-138 |
Date of Issue |
2007-12-06 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2007-138 Link to ES Tech. Rep. Archives: ICD2007-138 |
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