Paper Abstract and Keywords |
Presentation |
2007-12-14 09:15
A Study on Mutual Data Transfer Control Circuits for Self-Timed Web-Pipeline Kazuhiro Komatsu, Shuji Sannomiya, Makoto Iwata (Kochi Univ. of Tech.), Suguru Kameda, Kazuo Tsubouchi (Tohoku Univ.) ICD2007-129 Link to ES Tech. Rep. Archives: ICD2007-129 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The self-timed pipeline (STP) is one of the most promising SoC architectures achieving the efficient utilization of abundant transistors, ultra low power, and easy-to-design with signal integrity and low EMI. This paper proposes the concept of a self-timed (clockless) web-pipeline in which various pipelines are distributed and interconnected each other as if it were the web on a huge LSI chip. The paper also proposes a basic data-transfer-control circuit which realizes various combinations of flow-thru processing between pipelines on the web pipeline, and then shows a self-timed pipelined sorting LSI core as an example application of the proposed circuit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Self-timed circuit / Web-pipeline / Inter-pipeline transfer control / Pipelined sorting / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 382, ICD2007-129, pp. 53-58, Dec. 2007. |
Paper # |
ICD2007-129 |
Date of Issue |
2007-12-06 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2007-129 Link to ES Tech. Rep. Archives: ICD2007-129 |
Conference Information |
Committee |
ICD ITE-CE |
Conference Date |
2007-12-13 - 2007-12-14 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2007-12-ICD-ITE-CE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Study on Mutual Data Transfer Control Circuits for Self-Timed Web-Pipeline |
Sub Title (in English) |
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Keyword(1) |
Self-timed circuit |
Keyword(2) |
Web-pipeline |
Keyword(3) |
Inter-pipeline transfer control |
Keyword(4) |
Pipelined sorting |
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1st Author's Name |
Kazuhiro Komatsu |
1st Author's Affiliation |
Kochi University of Technology (Kochi Univ. of Tech.) |
2nd Author's Name |
Shuji Sannomiya |
2nd Author's Affiliation |
Kochi University of Technology (Kochi Univ. of Tech.) |
3rd Author's Name |
Makoto Iwata |
3rd Author's Affiliation |
Kochi University of Technology (Kochi Univ. of Tech.) |
4th Author's Name |
Suguru Kameda |
4th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
5th Author's Name |
Kazuo Tsubouchi |
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Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-12-14 09:15:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2007-129 |
Volume (vol) |
vol.107 |
Number (no) |
no.382 |
Page |
pp.53-58 |
#Pages |
6 |
Date of Issue |
2007-12-06 (ICD) |