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Paper Abstract and Keywords
Presentation 2007-11-22 14:55
An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems
Nozomu Hama, Hiroyuki Shimajiri, Takeo Yoshida (Univ. of the Ryukyus) VLD2007-100 DC2007-55
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we show an architecture of low density parity check (LDPC) decoders based on the Min-Sum algorithm for high speed WLAN systems.
The decoder supports twelve combinations of code lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4 , 5/6 based on IEEE 802.11n standard.
The total cell area of our decoder is
69,467,024 [\textrm{nm}$^2$].
Keyword (in Japanese) (See Japanese page) 
(in English) LDPC Code / IEEE 802.11n / Decoder / Min-Sum Algorithm / WLAN / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 336, VLD2007-100, pp. 67-72, Nov. 2007.
Paper # VLD2007-100 
Date of Issue 2007-11-15 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-100 DC2007-55

Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To VLD 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems 
Sub Title (in English)  
Keyword(1) LDPC Code  
Keyword(2) IEEE 802.11n  
Keyword(3) Decoder  
Keyword(4) Min-Sum Algorithm  
Keyword(5) WLAN  
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1st Author's Name Nozomu Hama  
1st Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
2nd Author's Name Hiroyuki Shimajiri  
2nd Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
3rd Author's Name Takeo Yoshida  
3rd Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
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Speaker Author-1 
Date Time 2007-11-22 14:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-100, DC2007-55 
Volume (vol) vol.107 
Number (no) no.336(VLD), no.339(DC) 
Page pp.67-72 
#Pages
Date of Issue 2007-11-15 (VLD, DC) 


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