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| Presentation | 2007-11-22 10:30 A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism Yuta Imai, Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)  RECONF2007-46 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, needs for downloading digital contents via wireless network have been dramatically increasing as high-functionalization of portable music player and mobile phone had proceeded and the digitalization of broadcasting had been done. For that reason it is now essential to support high communication quality in a situation where communication environment is unstable. Low Density Parity Check(LDPC) code is expected to be an error correcting code for next generation since it shows high error correcting performance. Many experiments have been carried out on this topic. At present LDPC code is incorporated in IEEE802.11n which is next standard of wireless network. In this paper, we propose area-saving LDPC decoder which can show a high decoding performance under unstalbe wireless communication environment. This is done by sharing adders within the column operational module among different information rates. Our method can also increase a parallelism of operation as an information rate gets higher so that the decoder shows higher decoding throughtput compared to the conventional decoders. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | LDPC Decoder / Irregular / Multi-Rate / column operation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 342, RECONF2007-46, pp. 19-24, Nov. 2007. | |
| Paper # | RECONF2007-46 | |
| Date of Issue | 2007-11-15 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2007-46 |
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| Conference Information | |
| Committee | VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2007-11-20 - 2007-11-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2007 ---A New Frontier in VLSI Design--- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism |
| Sub Title (in English) | |
| Keyword(1) | LDPC Decoder |
| Keyword(2) | Irregular |
| Keyword(3) | Multi-Rate |
| Keyword(4) | column operation |
| Keyword(5) | |
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| 1st Author's Name | Yuta Imai |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Kazunori Shimizu |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Masao Yanagisawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Tatsuo Ohtsuki |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-11-22 10:30:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2007-46 |
| Volume (vol) | vol.107 |
| Number (no) | no.342 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2007-11-15 (RECONF) |
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