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Paper Abstract and Keywords
Presentation 2007-11-22 15:45
Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor
Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-104 DC2007-59
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, spread of data intensive multimedia applications equires high-performance in embedded systems.
Massively Parallel Fine-grained SIMD Processor (MX), developed by Renesas Technology Corp., achieves high performance for digital signal processing using its high parallelism.
The execution cycles of MX, however, is greatly influenced by the way of the data assigned to the internal memory banks called MTA, and the orders of operands in the code of MTA.
In this paper, we propose Data Relational Hypergraph (DRH) and an optimization method for the memory assignment in MTA.
Keyword (in Japanese) (See Japanese page) 
(in English) MX / MTA / Combinatorial optimization / Memory assignment / Hypergraph / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 336, VLD2007-104, pp. 91-96, Nov. 2007.
Paper # VLD2007-104 
Date of Issue 2007-11-15 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-104 DC2007-59

Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To VLD 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor 
Sub Title (in English)  
Keyword(1) MX  
Keyword(2) MTA  
Keyword(3) Combinatorial optimization  
Keyword(4) Memory assignment  
Keyword(5) Hypergraph  
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1st Author's Name Akira Kobashi  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Ittetsu Taniguchi  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Hiroaki Tanaka  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Keishi Sakanushi  
4th Author's Affiliation Osaka University (Osaka Univ.)
5th Author's Name Yoshinori Takeuchi  
5th Author's Affiliation Osaka University (Osaka Univ.)
6th Author's Name Masaharu Imai  
6th Author's Affiliation Osaka University (Osaka Univ.)
7th Author's Name Kiyoshi Nakata  
7th Author's Affiliation Renesas Technology Corporation (Renesas)
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Speaker
Date Time 2007-11-22 15:45:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2007-104,IEICE-DC2007-59 
Volume (vol) IEICE-107 
Number (no) no.336(VLD), no.339(DC) 
Page pp.91-96 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2007-11-15,IEICE-DC-2007-11-15 


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