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Paper Abstract and Keywords
Presentation 2007-11-22 15:20
Retargetable Linear Assembler for VLIW Processor
Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.) VLD2007-103 DC2007-58
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a retargetable linear assembler
as a software development tool for custom VLIW processors.
The retargetable linear assembler takes a linear assembly program, which can be coded without the detailed knowledge of the microarchitecture, and architecture description of a target processor,
to generate an assembly code optimized for the processor.
We present an architecture model and the formulation of the scheduling problem for the retargetable linear assembler.
Keyword (in Japanese) (See Japanese page) 
(in English) retargetable linear assembler / VLIW processor / code scheduling / / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 336, VLD2007-103, pp. 85-90, Nov. 2007.
Paper # VLD2007-103 
Date of Issue 2007-11-15 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-103 DC2007-58

Conference Information
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Retargetable Linear Assembler for VLIW Processor 
Sub Title (in English)  
Keyword(1) retargetable linear assembler  
Keyword(2) VLIW processor  
Keyword(3) code scheduling  
1st Author's Name Satoshi Nogaito  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Nagisa Ishiura  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
3rd Author's Name Masaharu Imai  
3rd Author's Affiliation Osaka University (Osaka Univ.)
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Date Time 2007-11-22 15:20:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2007-103,IEICE-DC2007-58 
Volume (vol) IEICE-107 
Number (no) no.336(VLD), no.339(DC) 
Page pp.85-90 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2007-11-15,IEICE-DC-2007-11-15 

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