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| Presentation | 2007-11-22 09:25 Performance evaluation of reconfigurable architecture based on digit-serial computation Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)  RECONF2007-44 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have developed core architecture which has RISC processor and DS-HIE reconfigurable architecture. This architecture is called as Hybrid DS Core architecture (Hy-DiSC architecture). This paper evaluates the effect of DS-HIE architecture in the point of performance and transistor counts. The test program is JPEG encoding. And DS-HIE architecture accelerate DCT processing for JPEG encoding. In a execution of DCT, Hy-DiSC architecture achieves 4.32 times higher performances, compared with the execution time of RISC processor without accelerating by DS-HIE processor. And when Hy-DiSC architecture executed JPEG encoding, it achieves 1.55 times higher performance. Then the transistor counts of DS-HIE architecture is 1/11 times in comparison with one core in Core2 Duo processor. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamic Reconfigurable Architecture / Digit-serial / Benes Network / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 342, RECONF2007-44, pp. 7-12, Nov. 2007. | |
| Paper # | RECONF2007-44 | |
| Date of Issue | 2007-11-15 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2007-44 |
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| Conference Information | |
| Committee | VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2007-11-20 - 2007-11-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2007 ---A New Frontier in VLSI Design--- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance evaluation of reconfigurable architecture based on digit-serial computation |
| Sub Title (in English) | |
| Keyword(1) | Dynamic Reconfigurable Architecture |
| Keyword(2) | Digit-serial |
| Keyword(3) | Benes Network |
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| 1st Author's Name | Takuro Uchida |
| 1st Author's Affiliation | Hiroshima City University Graduate school (Hiroshima City Univ.) |
| 2nd Author's Name | Tetsuya Zuyama |
| 2nd Author's Affiliation | Hiroshima City University Graduate school (Hiroshima City Univ.) |
| 3rd Author's Name | Kazuya Tanigawa |
| 3rd Author's Affiliation | Hiroshima City University Graduate school (Hiroshima City Univ.) |
| 4th Author's Name | Tetsuo Hironaka |
| 4th Author's Affiliation | Hiroshima City University Graduate school (Hiroshima City Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-11-22 09:25:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2007-44 |
| Volume (vol) | vol.107 |
| Number (no) | no.342 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2007-11-15 (RECONF) |
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