Paper Abstract and Keywords |
Presentation |
2007-11-22 14:55
Cycle Partitioned Scheduling for Code Optimization of VLIW DSP Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2007-102 DC2007-57 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper proposes a cycle partitioned scheduling method for code optimization of VLIW DSPs. The previously proposed optimum code scheduling method for VLIW DSPs, which takes into account the capacity of registerfiles, insertion of data transfer operations, and operand asymmetry of functional units, required such an enormous computation cost that it can not handle large scale codes within a practical amount of time. Instead of processing a whole code at a time, our scheduler builds up entire scheduling by repeating computation for a fixed amount of cycles. This curbs the computation cost for each stage and allows optimization of the larger codes within feasible time, though the optimalty of the solution may not be guaranteed. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
clutered VLIW DSP / code optimization / TMS320C62x / cycle partitioned scheduling / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 336, VLD2007-102, pp. 79-84, Nov. 2007. |
Paper # |
VLD2007-102 |
Date of Issue |
2007-11-15 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2007-102 DC2007-57 |
Conference Information |
Committee |
VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC |
Conference Date |
2007-11-20 - 2007-11-22 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu International Conference Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2007 ---A New Frontier in VLSI Design--- |
Paper Information |
Registration To |
VLD |
Conference Code |
2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Cycle Partitioned Scheduling for Code Optimization of VLIW DSP |
Sub Title (in English) |
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Keyword(1) |
clutered VLIW DSP |
Keyword(2) |
code optimization |
Keyword(3) |
TMS320C62x |
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cycle partitioned scheduling |
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1st Author's Name |
Yuuki Masui |
1st Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
2nd Author's Name |
Nagisa Ishiura |
2nd Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-11-22 14:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2007-102, DC2007-57 |
Volume (vol) |
vol.107 |
Number (no) |
no.336(VLD), no.339(DC) |
Page |
pp.79-84 |
#Pages |
6 |
Date of Issue |
2007-11-15 (VLD, DC) |
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