講演抄録/キーワード |
講演名 |
2007-11-21 14:40
Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning ○Thomas Edison Yu・Tomokazu Yoneda(NAIST)・Krishnendu Chakrabarty(Duke Univ.)・Hideo Fujiwara(NAIST) VLD2007-84 DC2007-39 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
Higher power densities and the non-linear spatial distribution of heat of VLSI chips put greater emphasis on chip-packaging and temperature control during test. For system-on-chips, power-based scheduling algorithms are used to optimize tests while satisfying power budgets. However, it has been shown that power-constrained test scheduling does not ensure thermal safety due to the non-uniform power distribution across the chip. In this paper, we present a test schedule optimization method for system-on-chips using cycle-accurate power profiles for thermal simulation, test partitioning, and interleaving that ensures thermal safety while still optimizing the test schedule. Our method uses a simplified thermal-cost model and bin-packing algorithm to ensure that the maximum temperatures of SoCs with fixed TAM and core assignments satisfy the temperature constraints with minimum increases in test application time. |
キーワード |
(和) |
/ / / / / / / |
(英) |
SoC test / thermal constraint / wrapper design / TAM design / test scheduling / / / |
文献情報 |
信学技報, vol. 107, no. 338, DC2007-39, pp. 13-18, 2007年11月. |
資料番号 |
DC2007-39 |
発行日 |
2007-11-14 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
VLD2007-84 DC2007-39 |
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