Paper Abstract and Keywords |
Presentation |
2007-11-21 14:40
An approach to Place and Route challenges in Dynamic Reconfiguration Ryo Hidaka, Fuminori Kobayashi (Kyushu Inst. of Tech.), Minoru Watanabe (Shizuoka Univ.) RECONF2007-38 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, though the dynamically reconfigurable devices begin to be practical, these devices change the circuit with time, and traditional place-and-route techniques cannot be used.
To solve this problem, we have customized the place-and-route tool for FPGA for dynamic reconfiguration. That tool was developed by V.Betz of the Toronto university, emphasizing the problem of the wiring delay that was caused by processes miniaturization. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / ORGA / VPR / place-and-route / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 341, RECONF2007-38, pp. 13-17, Nov. 2007. |
Paper # |
RECONF2007-38 |
Date of Issue |
2007-11-14 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2007-38 |
Conference Information |
Committee |
VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC |
Conference Date |
2007-11-20 - 2007-11-22 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu International Conference Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2007 ---A New Frontier in VLSI Design--- |
Paper Information |
Registration To |
RECONF |
Conference Code |
2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An approach to Place and Route challenges in Dynamic Reconfiguration |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
ORGA |
Keyword(3) |
VPR |
Keyword(4) |
place-and-route |
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1st Author's Name |
Ryo Hidaka |
1st Author's Affiliation |
Kyusyu Institute of Technology (Kyushu Inst. of Tech.) |
2nd Author's Name |
Fuminori Kobayashi |
2nd Author's Affiliation |
Kyusyu Institute of Technology (Kyushu Inst. of Tech.) |
3rd Author's Name |
Minoru Watanabe |
3rd Author's Affiliation |
Shizuoka University (Shizuoka Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-11-21 14:40:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2007-38 |
Volume (vol) |
vol.107 |
Number (no) |
no.341 |
Page |
pp.13-17 |
#Pages |
5 |
Date of Issue |
2007-11-14 (RECONF) |
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